The arrangement of sense amplifiers in a semiconductor memory device is determined according to the bitline architecture of the semiconductor memory device. Bitline architectures that can be adopted in semiconductor memory devices include a folded bitline architecture and an open bitline architecture. A method of controlling the voltage of bitline pairs in a semiconductor memory device having an open bitline architecture after performing a sense amplification operation is disclosed in U.S. Pat. No. 5,953,275.
FIG. 1 is a block diagram of a semiconductor memory device that may be used to explain a sense operation performed by a semiconductor memory device having a folded bitline architecture. Referring to FIG. 1, the semiconductor memory device includes a plurality of memory cell arrays designated A (12), B (11), and C (13). The semiconductor memory device also includes a plurality of sense amplifier blocks 21, 22, and 23. Each of the sense amplifiers in the sense amplifier blocks 21, 22, and 23 is allocated to respective corresponding bitline pairs, each comprising a bitline BL and a bitline /BL.
When the memory cell array B (11) is activated, the bitlines BL and /BL in the memory cell array B (11) have opposite voltages. The sense amplifiers of the sense amplifier block 21 that are connected to the memory cell array B (11) sense that the bitlines BL have a high voltage (H) and that the bitlines /BL have a low voltage (L), and amplify a difference between the high voltage H and the low voltage L. The sense amplifier outputs the result of this amplification operation to complete the data sensing operation.
When the memory cell array B (11) is activated, the memory cell array A (12) and the memory cell array C (13), each of which are adjacent to the memory cell array B (11), are disconnected from the sense amplifier blocks 21. Therefore, all the bitline pairs in the memory cell array A (12) and in the memory cell array C (13) remain precharged (P).
FIG. 2 is a circuit diagram of a semiconductor memory device having a conventional open bitline architecture. Referring to FIG. 2, the semiconductor memory device includes a plurality of memory cell arrays 31 and 32, a plurality of sense amplifiers 40, and a plurality of precharge units 50. In FIG. 2, reference character CSL indicates a column selection line, and reference characters LANG and LAPG indicate a pull-down signal and a pull-up signal, respectively. The pull-down signal LANG is applied to the pull-down transistors MN of the sense amplifiers 40, and the pull-up signal LAPG is applied to the pull-up transistors MP of the sense amplifiers 40.
Each of the sense amplifiers 40 are connected between a Bitline of the first memory cell array 31 and a Bitline of the second memory cell array 32. For example, a sense amplifier 40 is connected between bitline BL1 of the first memory cell array 31 and bitline /BL1 of the second memory cell array 32, and performs a data sensing operation. When the first memory cell array 31 stores logic high data, the bitlines BL1 and/BL1 reach a high voltage and a low voltage, respectively.
If the sense amplifier 40 terminates the data sensing operation after a wordline W/L of the first memory cell array 31 is activated, the precharge unit 50 performs a precharge operation in response to a precharge control signal PEQ.
FIG. 3 is a diagram for explaining an embodiment of a sensing operation performed by a conventional semiconductor memory device having an open bitline architecture. Referring to FIG. 3, the semiconductor memory device includes 3 memory cell arrays B (31), A (32), and C (33) and a plurality of sense amplifier blocks 41, 42, 43, and 44.
FIG. 3 illustrates the voltages of bitlines included in the semiconductor memory device when the memory cell array B (31) is activated and has logic high data. When the memory cell array B (31) stores logic high data, the bitlines BL of the memory cell array B (31) all reach a high voltage (H). In the memory cell arrays A (32) and C (33), which are adjacent to the memory cell array B (31), only the bitlines that are connected to the sense amplifier blocks 41 and 42 of memory cell array B (31) reach a low voltage (L), and the other bitlines that are not connected to the sense amplifier blocks 41 and 42 remain precharged. Therefore, in the memory cell arrays A (32) and C (33), bitlines having the low voltage (L) and bitlines having a precharge voltage (P) coexist.
FIG. 4 is a diagram for explaining another embodiment of a sensing operation performed by a conventional semiconductor memory device having an open bitline architecture when a memory cell array B (31) of the semiconductor memory device is activated and has logic low data. FIG. 5 is a diagram for explaining a sensing operation performed by a conventional semiconductor memory device having an open bitline architecture when a memory cell array B (31) is activated and has both logic high data and logic low data.
Referring to FIG. 4, since the memory cell array B (31) has logic low data, all bitlines BL of the memory cell array B (31) reach a low voltage (L) when the memory cell array B (31) is activated. However, bitlines that are included in memory cell array A (32) that are connected to sense amplifier 42, as well as bitlines that are included in memory cell array C (33) that are connected to sense amplifier 41 reach a high voltage (H). Therefore, in the memory cell arrays A (32) and C (33), which are adjacent to the memory cell array B (31), bitlines having the high voltage H and bitlines having the precharge voltage (P) coexist.
Referring to FIG. 5, since the memory cell array B (31) has both logic low data and logic high data, the bitlines BL in memory cell array B (31) have a high voltage (H) or a low voltage (L). On the other hand, the bitlines included in memory cell array A (32) that are connected to sense amplifier 42 reach the high voltage (H). Other bitlines in memory cell array A (32) that are connected to sense amplifier 43 remain precharged (P). Therefore, in memory cell array A (32), bitlines having the high voltage (H) and bitlines having the precharge voltage (P) coexist. In addition, bitlines in memory cell array C (33) that are connected to sense amplifier 41 reach a low voltage (L). Therefore, in the memory cell array C (33), bitlines having the low voltage (L) and bitlines having the precharge voltage (P) coexist.
FIG. 6 is a waveform diagram illustrating a sensing operation performed by the semiconductor memory device of FIG. 2. The sensing operation will now be described in detail with reference to FIGS. 2 and 6. Referring to FIGS. 2 and 6, when a first cell block selection signal PBLSi for activating the memory cell array 31 is activated, the precharge control signal PEQ for controlling the precharge unit 50 is inactivated so that a precharge operation is terminated. The sense amplifier 40 performs a sensing operation in response to a sensing initiation signal PS. If the memory cell array 31 has logic high data, the bitlines BL1 and/BL1, which are connected to the sense amplifier 40, reach the high voltage (H) and the low voltage (L), respectively. In the memory cell array 32, which is adjacent to the memory cell array 31, the bitline /BL1 having the low voltage and a bitline BL3 having the precharge voltage (P) coexist.
As described above, in a memory cell array of a semiconductor memory device having a conventional open bitline architecture, both bitlines having a low voltage and bitlines having a precharge voltage, or both bitlines having a high voltage and bitlines having the precharge voltage, may coexist, if the memory cell array is a memory cell array that is not activated after a sensing operation.